The present invention relates generally to semiconductor memory devices and methods for making the same, and more particularly, to a novel stacked trench capacitor especially suitable for semiconductor memory devices having increased cell packing density, and a method for making the same.
It is generally well-known that significant advancements have been made in recent years with respect to increasing the cell packing density or integration level of semiconductor memory devices, such as dynamic random access memories (DRAMs). As a general rule, the memory capacity of DRAMs has been quadrupled approximately every three years. At the present time, 4 Mb DRAMs are in mass production, 16 Mb DRAMs are about to enter into mass production, 64 Mb DRAMs are in a later stage of development, and 256 Mb DRAMs are in an earlier stage of development.
In general, the chip surface area of semiconductor memory devices is increased by approximately 1.4X for each 4X increase in cell packing density thereof, which results in an approximately 1/3 reduction in the surface area available for each memory cell. Therefore, for each new generation of semiconductor memories, it has become necessary to increase the capacitance to surface area ratio of each memory cell in order to achieve sufficiently large memory cell capacitance. Past techniques for achieving this can be broadly classified into the following three categories:
(1) decreasing the thickness of the dielectric film of the memory cell capacitors;
(2) increasing the dielectric constant of the dielectric film; and,
(3) increasing the effective area of the storage electrode of the memory cell capacitors.
With respect to the first technique enumerated above, the lower practical limit of dielectric film thickness is approximately 100 .ANG., because the reliability of the memory cells becomes unacceptably degraded when the thickness of the dielectric film is less than 100 .ANG., due to the creation of Fowler-Nordheim currents. With respect to the second technique enumerated above, the most promising high dielectric constant dielectric film material is tantalum pentoxide (Ta.sub.2 O.sub.5), which provides good coverage with respect to three-dimensional memory cell structures having a high aspect ratio. However, tantalum pentoxide exhibits a high leakage current and a low breakdown voltage in a thin film state, thus limiting its utility with respect to the ultra-high capacity memories currently under development.
Consequently, the bulk of the current development efforts have been focused on the third technique enumerated above, namely, increasing the effective area of the storage electrode of the memory cell capacitors. Historically, as the need for memory cells having a large capacitance to surface area ratio has increased in parallel with the continuing development of memories having increased cell packing densities, the structure of memory cell capacitors has evolved from planar-type capacitors to three dimensional stack-type and trench-type capacitors, culminating at the present time in a stacked trench-type capacitor which is a hybrid of the stack-type and trench-type capacitors.
Since the stacked trench-type capacitor constitutes the current state-of-the-art in the field of memory cell capacitors, a pair of adjacent memory cells each including a capacitor of this type are depicted in FIG. 1, and will now be described with reference thereto. More particularly, each of the two memory cells depicted in FIG. 1 includes a transistor and a stacked trench capacitor, with the adjacent memory cells being separated by an isolation region of a P-type semiconductor substrate 100. As can be readily seen, the transistor of each memory cell is comprised of a drain region (only partially shown), a source region 3', and a gate electrode 2 separated from the upper surface of the semiconductor substrate 100 by a thin gate oxide layer 1, and spanning the separation between the source and drain regions, which defines the channel region of the transistor. The source and drain regions are formed in the upper surface of the semiconductor substrate 100 and define an active region of the semiconductor substrate 100. A field oxide layer 102 formed in the upper surface of the semiconductor substrate 100 between the adjacent memory cells defines the isolation region of the semiconductor substrate 100. An insulating layer 5 is formed on the gate electrode 2 of each memory cell and over the active and isolation regions of the semiconductor substrate 100.
Each memory cell further includes a stacked trench capacitor C constructed as follows. A trench 30 is formed in the upper surface of the semiconductor substrate 100 so as to extend to a predetermined depth below the upper surface of the semiconductor substrate 100. An N.sup.+ doped region 3 is formed in the surface portion of the semiconductor substrate 100 defining the trench 30 of each memory cell capacitor C, so that the doped region 3 extends along the interior surface of the trench 30 from the source region 3' of the transistor to the field oxide layer 102 between the adjacent memory cells. Next, a storage electrode SE is formed on the bottom surface and sidewalls of the trench 30 of each capacitor C, and on the insulating layer 5 of each transistor, to thereby provide a generally U-shaped storage electrode SE in contact with the N.sup.+ doped region 3. Then, a thin dielectric film 20 is formed on the entire outer surface of the storage electrode SE of each capacitor C. Finally, a plate electrode PE is formed on the thin dielectric film 20 of each capacitor C, and on the insulating layer 5 of each transistor, to thereby complete the stacked trench capacitor structure.
In the above-described semiconductor memory device utilizing conventional stacked trench type memory cell capacitors, if the length S of the isolation region between adjacent memory cells is shortened, the distance between the adjacent trenches 30 is commensurately reduced, thereby increasing the leakage current between adjacent memory cells and degrading the isolation characteristics of the overall semiconductor memory device. Further, the formation of the trenches 30 is achieved by etching, which can cause damage to the surface of the semiconductor substrate 100. Additionally, the N.sup.+ doped regions 3 are disadvantageously wide, thereby unduly increasing the leakage current from the capacitors C to the semiconductor substrate 100, which ultimately degrades the performance and reliability of the overall semiconductor memory device.
Based upon the above and foregoing, it can be appreciated that there presently exists a need in the semiconductor memory art for a semiconductor memory device which eliminates the above-described drawbacks and shortcomings of the presently available semiconductor memory devices. The present invention fulfills this need.